The Nuts and Bolts of Integrating PCIe Into Your Design

This white paper describes how to integrate a full PCI Express (PCIe) solution into your chip design. The paper summarizes types of integration, IP selection, lab set up, integration timelines, and future migration of the design. Engineers and managers will learn about potential integration issues and how to avoid them.

Types of Integration

There are essentially three levels of production that you can design for—low, medium, and high volume.

Field programmable gate arrays (FPGAs) are typically best suited for prototypes and low volume production, either with an internal PHY or with a recommended external third party PHY. Start-up costs of FPGA are very low, and parts can be purchased in single quantities. There are integration issues with FPGAs, and the path to volume production can be complex (also see ChipX white paper: Prototyping Physical Layer IP ASIC with FPGA).

If medium to high volume is expected, development can still take place using an FPGA, with a migration to an Application Specific Standard Product (ASSP) PCIe bridge or Mixed-signal ASIC. With a bridge chip, the end result will have surplus silicon, but the bridge chip is also the easiest solution for achieving volume production. If a chip has all the functionality and performance you need, simply buy it off the shelf!

Another medium to high volume solution is Mixed-signal ASIC. ASICs provide the exact functionality and performance you need, without sacrificing development time or introducing design risk. ASICs also provide a completely seamless path from prototype to production. For solutions where high volume production is expected from the outset, Standard Cell ASIC solutions are best. The upfront risk is much higher and time to market is much longer, but after the chip is in production, costs are lowest.

The Integration Process

The following integration process is simplified for purposes of this overview: 1.Select a PHY transceiver (or PHY IP, if you are going to develop on silicon) and Controller IP. 2.Integrate these IP blocks in the technology and design of choice. 3.Where applicable, make a test chip and PCB. Conduct lab tests.

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