Structured ASIC Overview

  * excluding USB 2.0 PHY pads
** excluding PHY pads

ChipX Structured ASICs are optimized for flexibility and fast time to market. They are also targeted at customers seeking an ASIC with a very low NRE. ChipX Structured ASICs combine built-in, silicon proven, industry standard configurable I/Os, memories and mixed signal IP with ChipX’s well-proven L-Cell and X-Cell™ configurable logic cells to provide industry leading performance using technology ranging from 5 V in 0.6µ process through advanced processes. Certain product families serve as platforms with pre-integrated and validated high-speed Phy interfaces and firm high-speed DDR and DDR2 memory interfaces. 

Features and Benefits

• Product families in 0.13µ HS, 0.18µ, 0.25µ and 0.35µ
• Pre-built configurable logic, memory and I/Os enable fast design implementations and rapid fabrication of the top layers of metal only.
• Re-spins and derivatives can be implemented quickly with re-synthesis and no time-consuming and risky ECOs.
• Up to 250 MHz maximum global operating frequency with greater than 20 levels of logic, 1 GHz local
• True ASIC gate count of up to 2 M usable gates using ChipX’s fine grain Structured ASIC logic fabric
• High speed, configurable embedded SRAM up to 2  Mbits. SRAM can be configured as single port, dual port or FIFO.
• DDR PHY up to 500 Mbps
• 1.2 V to 5 V core operating voltages
• Wide range of I/O options, including LVTTL, LVCMOS, HSTL, SSTL (18/2/3), LVDS (up to 840 Mbps), RSDS, PCI, PCI-X, XOSC, and others
• Commercial and Industrial grade temperature libraries. Military grade products are also available.
• Built-in configurable PLLs with Spread Spectrum tracking and output range of 10 MHz – 1 GHz
• Multiple DLLs with output frequency of up to 400 MHz can be placed in the logic area
• Packages from 40QFN to 896PBGA