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Structured ASIC Design Flow

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ChipX has exercised its Structured ASIC design flow over the course of a decade of experience delivering more than 1,500 Structured ASIC designs successfully to market. Following is an overview of our design flow.

Customer Deliverables

ChipX accepts designs in either RTL , gate-level Netlist or FPGA Netlist format.

Engineering Service Elements

ChipX uses standard tools throughout the design flow, enabling knowledge reuse as well as freedom from ties to proprietary tools. 

  • Simulation (NC-Verilog, Verilog-XL, VHDL, ModelSim)
  • Synthesis (Synopsys: DC Shell, DC Ultra; Magma: Blast Create; Synplicity: Synplify ASIC)
  • Formal Verification (Synopsys Formality)
  • RTL Analysis (Atrenta Spyglass)
  • Scan Insertion (Syntest)
  • Physical Design (Magma Blast Fusion)

Design Flow

The Structured ASIC design flow is similar to, but simpler than that of Standard Cell ASIC design. In the illustrated case of an RTL handoff below, elements in yellow are executed by ChipX engineering. The green elements are executed by the customer and white elements are conducted jointly by ChipX and the customer. 

  sa design flow.jpg
 

 

Project Schedule

A key consideration in all ASIC projects is time to market. Tested Structured ASICs prototypes are generally ready in six to nine weeks from handoff. This contrasts with a much longer standard cell lead time. Developers should expect to budget two to four weeks for the design process followed by four to five weeks for the prototype manufacturing cycle.

Typical Structured ASIC Project Schedule:

  • Handoff, Place and Router   2-4 weeks
  • Tested Protogypes               4-5 weeks
Packaging

 

ChipX has in excess of three hundred pre-tooled packages for our customers to choose from, or we will custom design a new package to meet the requirements of your specific application. 

By leveraging its long history of reusability in system design, most ChipX packages are standard, saving tooling and development costs as well as risk. ChipX has hundreds of standard package variations tooled for you to choose from. 

Test

All of ChipX's advanced Structured ASICs are tested using probe hardware designed to fit the masterslice rather than the application. This simplifies the development process, reducing risk and time to market for the designer. 

Summary

Delivering first time working silicon is essential in today's market. It means not only smooth execution, but also flexibility as market requirements evolve and target markets change. Having the flexibility to quickly build successive iterations of a design to address a specific customer requirement is possible and practical with the low turnaround time and resource requirements of Structured ASICs. ChipX's experienced engineering team will get you there.

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