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ChipX in the News

Benefits and Pitfalls of Data Converter ASIC Integration

February 2, 2009 ChipX Introduces 10-bit and 12-bit ADC IP Cores For Data Monitoring, Data Acquisition and Analog Front-Ends in ASICs

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CX6900 0.13 µ Standard Cell ASIC/SoC Product Brief

CX5900 0.18 µ Standard Cell ASIC/SoC Product Brief

CX4900 0.25 µ Standard Cell ASIC/SoC Product Brief

Part Number	Process	Usable Gates	Maximum Pads	Max System Clock (MHz)	5V Support	Core Voltage [V]	USB	PCIe	PLL
CX6900	0.13µ	12M	up to 896	333	x	1.2	Can include any mixed signal IP
CX5900	0.18µ	8M	up to 896	233		1.8
CX4900	0.25µ	5M	up to 896	150		2.5/3.3

ChipX uses Standard Cell ASIC technology to implement customer system-on-chip (SoC) designs that require a very high-level of integration with the lowest device cost possible and/or highest performance. ChipX can implement Standard Cell designs in 0.13µ, 0.18µ and 0.25µ, with 65 nm designs starting in second half 2008. ChipX has implemented complex designs with 10 M gates and up to 550 MHz with integrated mixed signal and analog IP. Visit our IP page for a list of available pre-validated IP Cores.

ChipX has a strong track record of first time working silicon with references available upon request. ChipX designers include unconnected spare cells to allow for potential bug fixes in metal and avoid costly re-spins. ChipX offers a Shuttle service for certain designs that require some IP to be validated first. Alternatively, customers can start with a Structured ASIC design first and ChipX will seamless migrate the design to a Standard Cell once the product and its market potential have been validated. This methodology is named XPath. This allows for a fast time to volume production with good risk mitigation. ChipX will credit a large portion of the Structured ASIC NRE toward the Standard Cell NRE to customers who choose to take advantage of this approach. Contact you ChipX representative for more details.

Easily and seamlessly convert from Structured ASIC to Standard Cell when volumes increase. The ChipX XPath methodology allows you to have the best of both worlds—start in a Structured ASIC (SA) and benefit from fast time to market and easy, low cost silicon changes—then convert to Standard Cell for optimal economy, and get credit for most of the SA NRE. XPath offers continuity in production, full reuse of previous design efforts, and significant simplification of design flow. Only one signoff is required from the customer.