Prototyping Physical Layer IP ASIC with FPGA

Many ASIC engineers incorporate an FPGA validation phase in their product development. Despite the many attractions of FPGA, it’s easy to fall into the trap of using easily accessible, yet proprietary, IP and various built-in structures such as multipliers, necessary to overcome the inherent FPGA performance limitations. This paper helps to avoid these pitfalls, and thus helps to create a smooth FPGA to mixed-signal ASIC migration for volume production.

Designing with FPGAs is relatively straightforward. Basic tools and hardware platforms are available to the developer for little or no money, so the design environment is easy to set up. The problem with using FPGA for mixed-signal ASIC prototyping has been the inability to include Physical IP that is not supported by the FPGA vendor.

Typically, the FPGA vendor solves this problem in one of two ways: first, a very high-end part is offered that includes IP with functionality similar to the desired IP, or second, a hardware platform that includes discrete components to make up for the lack in functionality in the FPGA is developed.

The first method forces the use of expensive parts; with the second method, it is no longer possible to verify the entire design using re-programmable parts. Specifically, an additional step in the mixed-signal ASIC integration cycle is required when migrating from an FPGA, because the designer needs to replace the physical IP or external interface and redesign logic as a result. The option to test the newly integrated RTL only exists in the final ASIC, requiring metal fixes or even a re-spin should anything go wrong. Also, most FPGAs contain substantial amounts of tempting, proprietary digital IP and structures, which are not available for use with technologies from other vendors.

The inability to include physical IP not supported by the FPGA vendor, and the FPGA containing proprietary IP and built-in structures introduces two painful realities: The design is no longer easily portable to a mixed-signal ASIC. The final product requires re- testing and re-verification to ensure any IP used to replace the FPGA structures works properly. ASIC companies have introduced hardware tools that alleviate the problems of IP portability, specifically for PHY IP. Using these platforms, designers can benefit from the speed and agility of FPGA prototyping, and in addition, they can design with the same PHY IP from the development stage through to final silicon. A typical ASIC Kit consists of two main components: A hardware platform, containing both a standard FPGA (for logic development), and test silicon containing the physical IP intended for future integration, and a software suite and library.

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