ChipX offers a full portfolio of silicon proven mixed-signal and analog IP to make your design integration simple and fast. ChipX develops its own mixed-signal and analog IP, and also works with a family of partners giving your design team the highest flexibility and choice in digital and analog IP selection.

Detailed Overview of Available ChipX IP

ARM926EJ Features

• 32-bit RISC processor with ARM®, Thumb® and DSP instruction sets
• ARM Jazelle technology delivers 8x Java acceleration
• 5-stage integer pipeline achieves 1.1 MIPS/MHz
• Up to 300 MIPS (Dhrystone 2.1) in a typical 130nm Standard Cell process
• Integrated real-time trace and debug support
• 215 MFLOPS for 3D graphics and real-time control systems
• High-performance AHB system
• MMU supporting Windows CE, Symbian OS, Linux, Palm OS
• Integrated instruction and data caches
• Real-time debug support for SoC designers, including ETM interface
• 16-entry write buffer — avoids stalling the processor when writes to external memory are performed
• Can be implemented in ChipX 130nm Embedded Array and Standard Cell products

Copyright Information
Copyright © ARM Ltd, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007. Copyright © Advanced RISC Machines Limited (ARM) 1995-1998. All rights reserved.

32 bit processors from Beyond Semiconductor

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Silicon proven in high volume production, the Beyond BA processors offer a powerful and economical alternative to other 32 bit architectures, covering everything from small footprint deeply embedded space to high performance DSP and floating point intensive applications. The processors are extensively verified and come with excellent industry standard SDK (software development kit including compiler, assembler,linker, debugger,...), software instruction set simulator and versatile OS support including latest Linux and eCos ports. Beyond Semiconductor and offersfree support as well as software and hardware design services necessary to quickly and effectively start using Beyond BA Processors.

BA Family of Processors:

• Features common to all Beyond BA Family of processors:
  • available with full RTL source
  • big and little endian support
  • configurable data and instruction caches
  • configurable MMU support with port to latest Linux
  • predictable execution rate for hard real-time applications
  • advanced debug unit with hardware breakpoints
  • real time execution trace buffer
  • integrated timer unit
  • integrated programmable interrupt unit
  • optional AHB or WISHBONE bus
  • numerous configuration options to achieve perfect combination of
  • size and performance
• Beyond BA12:
  • ARM9(tm) class processor
  • OpenRISC backwards compatible
  • 1.02 DMIPS/MHz (Dhrystone 2.1)
  • DSP and custom instructions
• Beyond BA22:
  • ARM11(tm) class processor
  • world highest code density in class, better then ARM Thumb2(tm)
  • dynamic frequency scaling, clock gating and sleep modes for minimal
  • power consumption
  • 1.36 DMIPS/MHz (Dhrystone 2.1)
  • advanced DSP and custom instructions
  • single precession fully IEEE 754 compliant FPU
• Beyond BA14/BA24:
  • ARM Cortex A8 (tm) class processor
  • superscalar, dual issue out-of-order execution for highest performance
  • 1.85 DMIPS/MHz (Dhrystone 2.1)
  • double precession, fully IEEE 754 compliant FPU
  • SIMD vector unit
  • advanced DSP and custom instructions
  • user configurable number of execution units
  • sophisticated branch prediction

Available are full FPGA development kits with reference SoC featuring chosen Beyond BAxx Processor, controllers and peripherals (DDR2 Controller, 10/100/1000 Ethernet Controller, DVI Display Controller, AC97 Controller, PS/2, UART). The reference SoC demonstration includes running latest Linux and eCos forming an excellent platform to debug and/or verify customer specific software and IP cores before going to volume production.

For more information please visit Beyond BA Evaluation Kit or request on-site demonstration by ChipX Sales.

DDR2/DDR SDRAM Memory Controller

• High performance, multiport AHB or WISHBONE Rev. B3 bus
• Compile time configurable number of chip select signals – two to four
• Software programmable chip select address range for each chip select – 8MB to 4GB
• Compile time configurable memory data bus width. Supported 16, 32 and 64 bits
• Utilization of write data mask signals for incomplete write bursts
• Compile time configurable memory address bus width
• Standard DDR and/or DDR2 SDRAM control interface
• External control signals for standard asynchronous static devices
• Software configurable external memory device data width for each chip select
• Supported widths are 8, 16, 32 and 64 bits for SDRAM devices and 8, 16 and 32 for asynchronous devices
• Register interface for software initiated SDRAM initialization sequence
• Support for asynchronous page mode static devices
• Software programmable burst sizes are 1, 2, 4 and 8
• Software programmable asynchronous static memory device timing parameters for every chip select
• Software programmable memory device timings
• Software programmable memory organization
• Independent of data transmit and capture implementation
• Pipelined, out-of-order memory command generation. Number of pipeline stages is selected at compile time according to application needs
• Automatic SDRAM refresh generation
• Register interface for software initialization and suspension of external memory devices
• Page tracking logic implemented to reduce access latencies. Tracked number of pages is selected at compile time according to application needs

MAC 10/100/1000 Ethernet Controller

• AHB or WISHBONE Rev. B3 bus
• Available with Linux software driver
• IEEE 802.3-2002 specification with preamble, start-of-frame delimiter (SFD), frame padding generation and cyclic redundancy code (CRC) generation and checking is fully implemented
• Supports 10/100 Mbps or 1000 Mbps operation (selectable via a core configuration registers)
• Supports full- and half-duplex operation (selectable via a core configuration   registers)
• CSMA/CD protocol for half-duplex operation
• Supports frame-extension in 1000 Mbps half-duplex mode
• IEEE 802.3x flow-control for full-duplex operation
• Variety of flexible address filtering modes
• Detection of too long or too short packets (configurable length limits)
• Supports transmission and reception of packets that are bigger than standard packets (up to 16-Kbyte)
• Complete status for TX/RX packets
• IEEE 802.3-2002 Media Independent Interface (MII) and Gigabit Media Independent Interface (GMII)
• MDIO Master interface for PHY device configuration and management
• Internal RAM for holding 128 TX/RX buffer descriptors
• Interrupt generation on all events

PCI 32 Bridge Controller

• AHB or WISHBONE Rev. B3 bus
• Available with Linux software driver
• PCI 2.2 compliant 32bit, 66MHz Initiator and Target interface
• Zero wait state burst operation
• Parameterized number of synthesizable, fully programmable images (default one, maximum 6 images) with address translation capability and 4KB to 1GB image size for access from PCI bus to address space on WISHBONE bus
• Programmable image address space mapping (I/O or memory space)
• PCI transaction ordering requirements; use of posted writes and delayed reads in either direction
• Single delayed transaction support in either direction
• Supported initiator functions:
• Memory Read, Memory Read Line, Memory Read Multiple, Memory Write commands
• IO Read and Write commands
• Configuration Read and Write commands:
• Interrupt Acknowledge command
• Support of linear burst ordering
• Supported Target functions:
• Memory Read, Memory Read Line, Memory Read Multiple, Memory Write, Memory Write and Invalidate commands
• IO Read and Write commands
• Configuration Read and Write commands
• Support of linear burst ordering
• Software configurable support for memory access optimizing commands
• Fully transparent WISHBONE interface operation, controllable on image by image basis with proper software settings of configuration registers

SDRAM/FLASH/SRAM Memory Controller

• AHB or WISHBONE Rev. B3 bus
• Pre-synthesis configurable number of chip select signals for asynchronous
• Pre-synthesis configurable number of chip select signals for synchronous dynamic devices. Maximum four
• Software programmable chip select address range for each chip select – 64KB to 2GB
• Pre-synthesis selectable external data bus width. Supported 8, 16, 32 and 64 bits
• Number of implemented byte mask signals depends on data bus width selection (1, 2, 4, or 8)
• Pre-synthesis selectable external address bus width
• External control signals for standard SDRAM memory devices
• External control signals for standard asynchronous static devices
• Software configurable external memory device data width for each chip select
• Supported widths are 8, 16, 32 and 64 bits for SDRAM devices and 8, 16 and 32 for asynchronous devices
• Register interface for software initiated SDRAM initialization sequence
• Support for asynchronous page mode static devices
• Possible SDRAM burst sizes are 1, 2, 4 and 8
• Software programmable asynchronous static memory device timing parameters for every chip select
• Software programmable SDRAM memory device timings
• Software programmable SDRAM memory organization
• Open row track keeping logic for SDRAM devices. Allows lower access latency
• Software programmable SDRAM address generation mode. Two modes are supported: Bank/Row/Column and Row/Bank/Column
• Automatic SDRAM refresh generation
• Register interface for software initiated suspend operation to external memory devices
• The data organization can be selected before synthesis and can be either big or little endian

VGA Display Controller

• AHB or WISHBONE Rev. B3 bus
• Available with Linux software driver
• Horizontal and vertical image scaling by integer factors
• CRT and LCD display support
• Separate VSYNC/HSYNC and composite CSYNC synchronization signals
• Composite BLANK signal
• User programmable video timing
• User programmable video resolutions
• User programmable video control signals polarity
• 32bpp, 24bpp and 16bpp color modes
• 8bpp grayscale and 8bpp pseudo-color modes
• Supports video bank switching during vertical retrace
  
  

AC97 Audio Controller

• AHB or WISHBONE Rev. B3 bus
• Available with Linux software driver
• AC97 Rev. 2.3 compliant
• Hardware variable sample rate support from 8kHz to 48kHz (up to 96kHz with Double Rate Audio enabled)
• Double Rate Audio support for Left, Right and Center channels
• 16 bit sample size support (18 and 20 bit support planned in future)
• Mono, stereo or multichannel (1, 2, 4 or 6 channels) audio output support
• Stereo Input and dedicated Mono microphone Input Channel support (all together 3 input channels)
• Power management support (individual subsections or full power-down mode)
• Full access to codec registers (tone, loudness, 3D stereo enhancement, etc.)

TAP Controller

• IEEE 1149.1-2001 compatible JTAG interface (TRST, TCK, TMS, TDI and TDO) to the external debugger / emulator testing device
• Supported instructions:
• All mandatory public instructions (BYPASS, SAMPLE/PRELOAD and EXTEST)
• Optional public instruction (IDCODE)
• Private instructions (DEBUG and MBIST)
• Supported scan chain registers:
• Internal Bypass register
• Internal ID register
• External Boundary Scan register
• External Debug Interface register
• External Memory BIST register

UART 16550 Serial Controller

• APB or WISHBONE bus
• Compatible with PC16550D / 16450
• FIFO depth of 16 bytes in 16650 mode
• Modem control functions
• Programmable serial interface
• Number of data bits (5 - 8)
• Number of stop bits
• 1 and 1, 5 for (5 data bits)
• 1 and 2 (6, 7, 8 data bits)
• False start bit detection
• Internal diagnostic (loopback, error simulation)
• Line break generation and detection
• Prioritized interrupts
• Readable Divisor latch value
• Readable transmitter and receiver FIFO fill levels

GPIO Controller

• APB or WISHBONE bus
• Number of general-purpose I/O signals is user selectable and can be in range from 1 to 32. For more I/Os several GPIO cores can be used in parallel
• All general-purpose I/O signals can be bi-directional (external bi-directional I/O cells are required in this case)
• All general-purpose I/O signals can be three-stated or open-drain enabled (external three-state or open-drain I/O cells are required in this case)
• General-Purpose I/O signals programmed as inputs can cause an interrupt request to the CPU
• General-purpose I/O signals programmed as inputs can be registered at raising edge of system clock or at user programmed edge of external clock
• All general-purpose I/O signals are programmed as inputs at hardware reset
• Auxiliary inputs to GPIO core to bypass outputs from RGPIO_OUT register
• Alternative input reference clock signal from external interface

Extremely configurable (implementation of registers, external clock inverted versus negedge flip-flops etc.)

8051 Processor

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• 8-bit Control Unit
• 8-bit Arithmetic-Logic Unit with 8-bit multiplication and division
• Instruction decoder
• Four 8-bit Input/Output ports
• Two 16-bit Timer/Counters
• Serial Peripheral Interface in full duplex mode
• Synchronous mode, fixed baud rate
• 8-bit & 9-bit UART mode, variable baud rate
• 9-bit UART mode, fixed baud rate
• Multiprocessor communication
• Two Level Priority Interrupt System
• 5 Interrupt Sources
• Internal Clock prescaler and Phase Generator
• 256 bytes of Read/Write Data Memory Space
• 64KB External Program Memory Space
• 64KB External Data Memory Space
• Services up to 107 External Special Function Registers
• Power Management Unit supports stop and idle modes
• On-Chip-Instrumentation Debugging (optional)

USB PHY

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The USB 2.0 compliant HS OTG PHY, in combination with ChipX validated, synthesizable processors and USB Host, Device, and OTG controllers, form a complete, interoperability-proven, USB subsystem capable of achieving USB-IF compliance. You can also use your own USB controller, and processor of choice where desired. The USB subsystem on the CX6200 family of products removes the complexity and risk of IP selection and IP interoperability testing, enabling faster time to market.

PCIe PHY

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The PCI Express PHY, in combination with the ChipX synthesizable processors and PCI Express endpoint, root port, or bridge controllers, form a complete PCI Express subsystem capable of achieving PCI-SIG compliance. You can also use your own PCI Express controller where desired. The PCI Express subsystem on the CX6100 family of products removes complexity and the risk of IP selection and IP interoperability testing.

DDR Controller

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CX6000 Synchronous Dynamic Random Access Memory Double Data Rate PHY. The SDRAM DDR PHY is implemented using ChipX X-Cells™ only, and is provided as a GDS firm macro, having a fixed layout but not a fixed placement. The ChipX DDR PHY can be placed next to any configurable I/O banks on a ChipX Structured ASIC product, providing unprecedented flexibility in choosing DDR interfaces.
1.1 Supported Standards
By choosing the appropriate I/O cells and cell configuration during the design, the ChipX DDR PHY can be used in systems that support either DDR or DDRII applications. The ChipX DDR/DDRII PHY supports speeds up to 667Mbps, depending on implementation.

PCIe Controller

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PCI Express controller cores are available as Soft IP from ChipX for inclusion in your design. The PCI Express controller core supports 1, 4, or 8 lanes and implements all protocol layers (Physical, Data Link and Transaction). The core supports root port, bridge or endpoint and interfaces to the PHY using the Intel PIPE interface. The controller core is delivered with simulation models, testbench, synthesis models, as well as a customization wizard and software drives. This product has passed PCI-SIG certification.

ChipX can supply PCI Express verification solutions for system verification and design.

10/100 Ethernet MediaAccess Controller Lite Core

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• Network interface features
  • Supports 10/100Mb/s data transfer rates
  • Media Independent Interface (MII)
• Data link layer functionality
  • Meets the IEEE 802.3 CSMA/CD standard
  • Full or half duplex operation
  • Flexible address filtering
  • External RAM for storing MAC-L addresses
  • Up to 16 physical addresses
  • 512 bit hash table for multicast addresses
  • External CAM interface
• Transmit/Receive dual port RAM interfaces
  • Operates as internal configurable FIFOs
  • Programmable threshold levels
  • "Store and forward" functionality
• Optional RMII interface

MIL-STD-1553 Interface

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ChipX offers a complete system solution for Avionics and Ground vehicle MIL-STD-1553. Our solution has been implemented in silicon and fully certified by third parties. We offer full RTL IP, that can be implemented in FPGA for prototypes and ASIC for production. RT and dual RT are supported at 1Mbps or 10Mbps; drive can be multi-drop RS485 using an external transciever. In order to certify interoperability, ChipX also offers third party RT testing services.

UART

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• Capable of running all existing 16450 and 16550a software
• Fully Synchronous design. All inputs and outputs are based on the rising edge of clock
• In FIFO mode, transmitter and receiver are each buffered with up to 256 byte FIFO's to reduce the number of interrupts presented to the CPU
• Available with FIFO sizes of 8, 16, 32, 64, 128 or 256 bytes
• Adds or strips standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• Programmable baud generator divides any input clock by 1 to (216 — 1) and generates the 16 x clock
• Modem control functions (CTSn, RTSn, DSRn, DTRn, and DCDn)
• Programmable Auto-CTSn and Auto-RTSn
• In Auto-CTSn mode, CTSn controls the transmitter
• In Auto-RTSn mode, the receiver FIFO contents and threshold control RTSn
• Fully programmable serial interface characteristics:
  • 5, 6, 7, or 8 bit characters
  • Even, odd, or no-parity bit generation and detection
  • 1, 1½, or 2 stop bit generation
  • Baud generation
• False start-bit detection
• Complete status register
• Internal diagnostic capabilities: loop-back controls for communications link fault isolation
• Full prioritized interrupt system controls

SDR-SDRAM

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• Interfaces directly to Mobile and ordinary Single Data Rate (SDR) SDRAM chips and registered/unbuffered DIMMS
• Supports address space up to 2G (2³⁰ words) and
  • one to eight chip selects,
  • two to four banks,
  • eleven to fourteen row bits,
  • eight to twelve column bits
• Manages up to four 2GB DIMMs
• Automatically generates initialization and refresh sequences
• Efficient bank management and access cascading for up to 100% memory throughput utilization
• Programmable automatic refresh policy reduces refresh overhead
• Runtime-configurable features for application flexibility
• timing parameters: CAS latency, tRP, tRCD, tREFC, tMRD, etc.
• memory settings: Row bits, Column bits, Bank bits, number of CSs
• Mobile-SDR support and Extended-Mode-Register (EMR) values
• Bank status monitoring means banks are opened or closed only when necessary, minimizing access delays
• Configurable auto-close mechanism minimizes power dissipation by precharging inactive banks
• Configurable auto power-down and auto-self-refresh: SDR devices put in power-down mode after some time of inactivity, and in self-refresh mode after a further time of inactivity.
• Energy-saving sleep-mode: after setting SDRAM devices in self-refresh mode, core "turns off" most of the internal circuitry to minimize power dissipation
• Flexible user-interface: separate read and write interfaces support from single to any arbitrary length burst accesses; access lengths defined using an access-size bus and/or a burst-stop signal.
• Easily interfaced to legacy on-chip synchronous microprocessor buses that support burst-accesses and handshaking, or to on-chip FIFOs (respective wrappers available on request)

DDR

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• High memory throughput achieved via Look-Ahead command processing, Bank Management and Auto-Precharge support
• Multi-Port Front-End supports high efficiency command reordering and multi-port interface
• ECC, RMW, and Multi-Burst add-on modules available
• Achieves high clock rates with minimal routing constraints
• Supports all standard DDR SDRAM chips and DIMMs
• Run-time configurable timing parameters and memory settings
• A variety of read capture options are supported
• Automatic generation of initialization and refresh sequences
• Supports self-refresh and powerdown modes
• Source code available
• Customization and Integration services available

DDR2

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• High memory throughput achieved via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
• Multi-Port Front-End supports high efficiency command reordering and multi-port interface
• ECC, RMW, and Multi-Burst add-on modules available
• Achieves high clock rates with minimal routing constraints
• Supports all standard DDR2 SDRAM chips and DIMMs
• Run-time configurable timing parameters and memory settings
• Full support of ODT and 2T timing
• A variety of read capture options are supported
• Automatic generation of initialization and refresh sequences
• Supports self-refresh and powerdown modes
• Source code available
• Customization and Integration services available

DMA

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8237 Compatible Programmable DMA Controller Core

• Enable/Disable control of individual DMA requests
• Four, independent DMA channels
• Independent auto-initialization of all channels
• Memory-to-Memory transfers
• Memory block initialization
• Address increment of decrement
• Directly expandable to any number of channels
• End of process input for terminating transfers
• Software DMA requests
• Independent polarity control for DREQ and DACK signals
• Approximately 5,500 gates depending on the technology used
• Functionality based on the Intel 8237

82380 Compatible 32-bit DMA Controller Core

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• Eight independently programmable channels of 32-Bit DMA
• Twenty source, individually programmable Interrupt channels
  • Fifteen external interrupts
  • 5 internal interrupts
  • Intel 8259 superset
• Four 16-Bit Programmable Interval Timers
  • Intel 8254 compatible
• Programmable Wait State generator
  • 0 to 15 Wait states Pipelined
  • 1 to 16 Wait states Non-Pipelined
• DRAM Refresh Controller
• The C82380 is available in VHDL and Verilog.
• Functionally based on the Intel 82380 device

I2C

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Slave

• Uses two wires to transfer information between devices
  • Serial Clock Line SCL (SCL)
  • Serial Data Line (SDA).
• Performs serial transmission with data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
• Slave Receiver Mode — Serial data and the serial clock are received through SDA and SCL
• Slave Transmitter Mode — Serial data is transmitted via SDA while the serial clock is input through SCL
• Bi-directional data transfer
• Own address and General Call address detection
• 7 bit addressing format
• Fixed data width of 8 bits
• Data transfer in multiples of bytes
• One-byte write and read buffer
• Strictly synchronous design with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward

Master/Slave

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• Uses two wires to transfer information between devices
  • Serial Clock Line SCL (SCL)
  • Serial Data Line (SDA).
• Performs serial transmission with data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
• Slave Receiver Mode — Serial data and the serial clock are received through SDA and SCL
• Slave Transmitter Mode — Serial data is transmitted via SDA while the serial clock is input through SCL
• Bi-directional data transfer
• Own address and General Call address detection
• 7 bit addressing format
• Fixed data width of 8 bits
• Data transfer in multiples of bytes
• One-byte write and read buffer
• Strictly synchronous design

High Speed

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• The I2C Bus uses two wires to transfer information between devices connected to the bus: SCL (serial clock line) and SDA (serial data line)
• Compliant to version 2.1 of the I2C Bus standard
• PVCI standard compliant (OCB 2 2.0)
• Data transfers up to 100 Kbps in standard mode, up to 400 Kbps in fast-mode, and up to 3.4 Mbps in high-speed mode
• Master Transmitter Mode — Serial data output through SDA while SCL outputs the serial clock
• Master Receiver Mode — Serial data is received via SDA while SCL outputs the serial clock
• Slave Receiver Mode — Serial data and the serial clock are received through SDA and SCL
• Slave Transmitter Mode — Serial data is transmitted via SDA while the serial clock is input through SCL
• Mixed-speed bus system configuration support
• Multimaster Mode

GPIO

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• Eight individually programmable input/output pins
• Programmable interrupt generation capability
• Bit masking in both read and write operations

Timer

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8254 Compatible Programmable Timer/Counter Core

• Three Independent 16-bit Counters
• Status Read-Back Command
• Counter Latch Command
• Read/Write LSB only or MSB only or LSB first then MSB
• Six Programmable Counter Modes
• Interrupt on Terminal Count
• Hardware Retriggerable One-Shot
• Rate Generator
• Square Wave Mode
• Software Triggered Strobe
• Hardware Triggered Strobe (Retriggerable)
• Binary or BCD Counting
• The C8254 was developed in HDL and synthesizes to approximately 4,200 gates depending on the technology used
• Functionality based on the INTEL 8254

SPI

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Master/slave

• Fully synchronous design with one clock domain
• Full duplex, synchronous, 8-bit serial data transfer
• High bit rates
• Master or slave mode
• Bit rates generated in Master mode:
  ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128, ÷256 of the system clock
• Bit rates supported in Slave mode: f_SCK < =f_SYSCLK ÷2
• Eight Slave Select lines
• MSB first or LSB first data transfer
• Technology independent HDL source code (soft core)