ChipX uses Standard Cell ASIC technology to implement customer system-on-chip (SoC) designs that require a very high-level of integration with the lowest device cost possible and/or highest performance.  ChipX can implement Standard Cell designs in 0.13u, 0.18u and 0.25u, with 65nm designs starting in second half 2008.  ChipX has implemented complex designs with 10M gates and up to 550MHz with integrated mixed signal and analog IP.  Visit our IP page for a list of available pre-validated IP cores. ChipX has a strong track record of first time working silicon with references available upon request. .  ChipX designers include unconnected spare cells to allow for potential bug fixes in metal and avoid costly re-spins.  ChipX offers a Shuttle service for certain designs that require some IP to be validated first.  Alternatively, customers can start with a Structured ASIC design first and ChipX will seamless migrate the design to a Standard Cell once the product and its market potential have been validated.  This methodology is named XPath. This allows for a fast time to volume production with good risk mitigation.  ChipX will credit a large portion of the Structured ASIC NRE toward the Standard Cell NRE to customers who choose to take advantage of this approach.  Contact you ChipX representative for more details.