Log In
Register
ChipX Locations
Maps and Directions
US Sales
Europe Sales
Asia Pacific Sales
Japan Sales
Tech Support
Overview
Download Center
PLL Compiler
IP Integration
White Papers
Chip(x)
My ChipX Technical Resources Contact Us
Products products
Products Print Page


ChipX offers the broadest portfolio of distinct paths to ASIC for your design with families comprised of technology ranging from 0.6µ through 0.13µ supporting designs of up to 10M gates. Based on your need for time to market, unit price and NRE, ChipX offers Structured ASIC, Embedded Array and Standard Cell ASIC solutions that can optimize your specific mix of requirements. Targeted for consumer, industrial, networking, medical, military and aerospace, ChipX has a path to ASIC that's ideal for you.

Structured ASIC 
 Family Process Max
Usable Gates
Embedded
Memory
(k bits)
Total
Pads
USB PCI PLL Core
Voltage
(v)
Max
System
Clock
(MHz)
5V
Support
ITAR
Compliant
CX6200 0.13µ 140K -685K 216-324 120-200* OTG/Device PCI, PCI-X 4-7 1.2 250    √
CX6100 0.13µ 350K-1.7M 288-1800 138-336** USB/FS PCI, PCI-X, PCIe 4-7 1.2 250    √
CX5000 0.18µ 90K-578K 160-1,264 256-768 FS PCI, PCI-X 4 1.8 200    √
CX4000 0.25µ 20K - 550K 0-448 128-1,024 FS PCI, PCI-X 4 1.8/2.5 150    √
CX3000 0.35µ 21K -200K 32-352 128-512   PCI (3V/5V) 1 3.3/5 50

* excluding USB 2.0 PHY pads
** excluding PHY pads


Embedded Array

 Family Process Max
Usable Gates
Total
Pads
Core
Voltage
(v)
Max
System
Clock
(MHz)
5V
Support
ITAR
Compliant
CX6500 0.13µ 8M up to 896 1.2 300    √


* Max usable gates is reduced in proportion to the inclusion of embedded RAM

Hybrid ASIC

Part Number Process Usable
Gates
Maximum
Pads
Max
System
Clock
(MHz)
5V
Support
Core
Voltage
[V]
USB PCIe PLL
CX6800 0.13µ 12M up to 896 333 x 1.2 Can include any
mixed signal IP


Standard Cell
 Family Process Max
Usable Gates
Total
Pads
Core
Voltage
(v)
Max
System
Clock
(MHz)
5V
Support
ITAR
Compliant
CX6900  0.13µ 12M up to 896 1.2 333  √
CX5900 0.18µ 8M up to 896 1.8 233    √
CX4900 0.25µ 5M up to 896 2.5/3.3 150    √

*Max usable gates is reduced in proportion to the inclusion of embedded RAM