Peripheral IP

 
UART

• Capable of running all existing 16450 and 16550a software
• Fully Synchronous design. All inputs and outputs are based on the rising edge of clock
• In FIFO mode, transmitter and receiver are each buffered with up to 256 byte FIFO's to reduce the number of interrupts presented to the CPU
• Available with FIFO sizes of 8, 16, 32, 64, 128 or 256 bytes
• Adds or strips standard asynchronous communication bits (start, stop and parity) to or from the serial data
• Independently controlled transmit, receive, line status and data set interrupts
• Programmable baud generator divides any input clock by 1 to (216 — 1) and generates the 16 x clock
• Modem control functions (CTSn, RTSn, DSRn, DTRn, and DCDn)
• Programmable Auto-CTSn and Auto-RTSn
• In Auto-CTSn mode, CTSn controls the transmitter
• In Auto-RTSn mode, the receiver FIFO contents and threshold control RTSn
• Fully programmable serial interface characteristics:
  • 5, 6, 7, or 8 bit characters
  • Even, odd, or no-parity bit generation and detection
  • 1, 1½, or 2 stop bit generation
  • Baud generation
• False start-bit detection
• Complete status register
• Internal diagnostic capabilities: loop-back controls for communications link fault isolation
• Full prioritized interrupt system controls

SDR-SDRAM

• Interfaces directly to Mobile and ordinary Single Data Rate (SDR) SDRAM chips and registered/unbuffered DIMMS
• Supports address space up to 2G (230 words) and
  • one to eight chip selects,
  • two to four banks,
  • eleven to fourteen row bits,
  • eight to twelve column bits
• Manages up to four 2GB DIMMs
• Automatically generates initialization and refresh sequences
• Efficient bank management and access cascading for up to 100% memory throughput utilization
• Programmable automatic refresh policy reduces refresh overhead
• Runtime-configurable features for application flexibility
• timing parameters: CAS latency, tRP, tRCD, tREFC, tMRD, etc.
• memory settings: Row bits, Column bits, Bank bits, number of CSs
• Mobile-SDR support and Extended-Mode-Register (EMR) values
• Bank status monitoring means banks are opened or closed only when necessary, minimizing access delays
• Configurable auto-close mechanism minimizes power dissipation by precharging inactive banks
• Configurable auto power-down and auto-self-refresh: SDR devices put in power-down mode after some time of inactivity, and in self-refresh mode after a further time of inactivity.
• Energy-saving sleep-mode: after setting SDRAM devices in self-refresh mode, core "turns off" most of the internal circuitry to minimize power dissipation
• Flexible user-interface: separate read and write interfaces support from single to any arbitrary length burst accesses; access lengths defined using an access-size bus and/or a burst-stop signal.
• Easily interfaced to legacy on-chip synchronous microprocessor buses that support burst-accesses and handshaking, or to on-chip FIFOs (respective wrappers available on request)

DMA

8237 Compatible Programmable DMA Controller Core

• Enable/Disable control of individual DMA requests
• Four, independent DMA channels
• Independent auto-initialization of all channels
• Memory-to-Memory transfers
• Memory block initialization
• Address increment of decrement
• Directly expandable to any number of channels
• End of process input for terminating transfers
• Software DMA requests
• Independent polarity control for DREQ and DACK signals
• Approximately 5,500 gates depending on the technology used
• Functionality based on the Intel 8237

82380 Compatible 32-bit DMA Controller Core

• Eight independently programmable channels of 32-Bit DMA
• Twenty source, individually programmable Interrupt channels
  • Fifteen external interrupts
  • 5 internal interrupts
  • Intel 8259 superset
• Four 16-Bit Programmable Interval Timers
  • Intel 8254 compatible
• Programmable Wait State generator
  • 0 to 15 Wait states Pipelined
  • 1 to 16 Wait states Non-Pipelined
• DRAM Refresh Controller
• The C82380 is available in VHDL and Verilog.
• Functionally based on the Intel 82380 device

Slave

• Uses two wires to transfer information between devices
  • Serial Clock Line SCL (SCL)
  • Serial Data Line (SDA).
• Performs serial transmission with data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
• Slave Receiver Mode — Serial data and the serial clock are received through SDA and SCL
• Slave Transmitter Mode — Serial data is transmitted via SDA while the serial clock is input through SCL
• Bi-directional data transfer
• Own address and General Call address detection
• 7 bit addressing format
• Fixed data width of 8 bits
• Data transfer in multiples of bytes
• One-byte write and read buffer
• Strictly synchronous design with positive-edge clocking, no internal tri-states and a synchronous reset; therefore scan insertion is straightforward

Master/Slave

• Uses two wires to transfer information between devices
  • Serial Clock Line SCL (SCL)
  • Serial Data Line (SDA).
• Performs serial transmission with data transfers up to 100 Kbps in standard mode and up to 400 Kbps in fast-mode
• Slave Receiver Mode — Serial data and the serial clock are received through SDA and SCL
• Slave Transmitter Mode — Serial data is transmitted via SDA while the serial clock is input through SCL
• Bi-directional data transfer
• Own address and General Call address detection
• 7 bit addressing format
• Fixed data width of 8 bits
• Data transfer in multiples of bytes
• One-byte write and read buffer
• Strictly synchronous design

  High Speed

• The I2C Bus uses two wires to transfer information between devices connected to the bus: SCL (serial clock line) and SDA (serial data line)
• Compliant to version 2.1 of the I2C Bus standard
• PVCI standard compliant (OCB 2 2.0)
• Data transfers up to 100 Kbps in standard mode, up to 400 Kbps in fast-mode, and up to 3.4 Mbps in high-speed mode
• Master Transmitter Mode — Serial data output through SDA while SCL outputs the serial clock
• Master Receiver Mode — Serial data is received via SDA while SCL outputs the serial clock
• Slave Receiver Mode — Serial data and the serial clock are received through SDA and SCL
• Slave Transmitter Mode — Serial data is transmitted via SDA while the serial clock is input through SCL
• Mixed-speed bus system configuration support
• Multimaster Mode

 GPIO

• Eight individually programmable input/output pins
• Programmable interrupt generation capability
• Bit masking in both read and write operations

Timer

 8254 Compatible Programmable Timer/Counter Core

• Three Independent 16-bit Counters
• Status Read-Back Command
• Counter Latch Command
• Read/Write LSB only or MSB only or LSB first then MSB
• Six Programmable Counter Modes
• Interrupt on Terminal Count
• Hardware Retriggerable One-Shot
• Rate Generator
• Square Wave Mode
• Software Triggered Strobe
• Hardware Triggered Strobe (Retriggerable)
• Binary or BCD Counting
• The C8254 was developed in HDL and synthesizes to approximately 4,200 gates depending on the technology used
• Functionality based on the INTEL 8254

Master/slave

• Fully synchronous design with one clock domain
• Full duplex, synchronous, 8-bit serial data transfer
• High bit rates
• Master or slave mode
• Bit rates generated in Master mode:
  ÷2, ÷4, ÷8, ÷16, ÷32, ÷64, ÷128, ÷256 of the system clock
• Bit rates supported in Slave mode: fSCK < =fSYSCLK ÷2
• Eight Slave Select lines
• MSB first or LSB first data transfer
• Technology independent HDL source code (soft core)

DDR

• High memory throughput achieved via Look-Ahead command processing, Bank Management and Auto-Precharge support
• Multi-Port Front-End supports high efficiency command reordering and multi-port interface
• ECC, RMW, and Multi-Burst add-on modules available
• Achieves high clock rates with minimal routing constraints
• Supports all standard DDR SDRAM chips and DIMMs
• Run-time configurable timing parameters and memory settings
• A variety of read capture options are supported
• Automatic generation of initialization and refresh sequences
• Supports self-refresh and powerdown modes
• Source code available
• Customization and Integration services available

DDR2

• High memory throughput achieved via Look-Ahead command processing, Bank Management, Auto-Precharge and Additive Latency support
• Multi-Port Front-End supports high efficiency command reordering and multi-port interface
• ECC, RMW, and Multi-Burst add-on modules available
• Achieves high clock rates with minimal routing constraints
• Supports all standard DDR2 SDRAM chips and DIMMs
• Run-time configurable timing parameters and memory settings
• Full support of ODT and 2T timing
• A variety of read capture options are supported
• Automatic generation of initialization and refresh sequences
• Supports self-refresh and powerdown modes
• Source code available
• Customization and Integration services available

  Network interface features

• • Supports 10/100Mb/s data transfer rates
  • Media Independent Interface (MII)
• Data link layer functionality
  • Meets the IEEE 802.3 CSMA/CD standard
  • Full or half duplex operation
  • Flexible address filtering
  • External RAM for storing MAC-L addresses
  • Up to 16 physical addresses
  • 512 bit hash table for multicast addresses
  • External CAM interface
• Transmit/Receive dual port RAM interfaces
  • Operates as internal configurable FIFOs
  • Programmable threshold levels
  • "Store and forward" functionality
• Optional RMII interface

MIL-STD-1553 Interface

 ChipX offers a complete system solution for Avionics and Ground vehicle MIL-STD-1553. Our solution has been implemented in silicon and fully certified by third parties. We offer full RTL IP, that can be implemented in FPGA for prototypes and ASIC for production. RT and dual RT are supported at 1Mbps or 10Mbps; drive can be multi-drop RS485 using an external transciever. In order to certify interoperability, ChipX also offers third party RT testing services.

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