|
CX6800 Hybrid ASIC Product Brief
Part Number
|
Process |
Usable
Gates |
Maximum
Pads |
Max
System
Clock
(MHz) |
5V
Support |
Core
Voltage
[V] |
USB |
PCIe |
PLL |
| CX6800 |
0.13µ |
12M |
up to 896 |
333 |
x |
1.2 |
Can include any
mixed signal |
The ChipX Hybrid ASIC is a standard cell implementation optimized for density and it includes an integrated, pre-defined Structured ASIC core. The Structured ASIC core is treated like any other hard macro on the die. ChipX can customize the macro to have any gate size and shape on the die. Customers identify a portion of the design that is subject to change in the future and wish to have it implemented in the Structured ASIC macro. Customers benefit from re-usability, low NREs for derivative products and fast re-spins. Typical applications include systems that require a variety of video compression schemes, data encryption and pre-standard protocol implementations.
Features and Benefits
- Implementation available in 0.13µ process
- Island of configurable logic can operate with a system clock of up to 300MHz with more than 20 levels of logic.
- Customized high density, high performance memory
- Wide range of I/O options, including LVTTL, LVCMOS, HSTL, SSTL (18/2/3), LVDS (up to 840 Mbps), RSDS, PCI, PCI-X, XOSC, and others
- True ASIC gate count of up to 12 M usable gates and 10Mbits of memory
- Core operating voltage of 1.2 V
- Commercial and Industrial grade temperature libraries
- Configurable PLLs with Spread Spectrum tracking, output range of 10 MHz – 1 GHz
- Multiple DLLs with output frequency of up to 400 MHz can be placed in the logic area.
- Packages from 40QFN to 896PBGA
- Fast re-spin of Structured ASIC core in 4-6 weeks
- Low re-spin and derivative NRE
- Mixed-Signal IP can be integrated in any Hybrid ASIC
|
