CX6200 Structured ASIC

CX6200 Structured ASIC USB HS 2.0 OTG Datasheet   

The CX6200 product family combines built-in, silicon proven, industry standard PHYs for USB 2.0 Hi-Speed On-the-Go (OTG) with the well-proven X-Cell™ Structured ASIC architecture, to provide industry-leading performance using the UMC eight-metal high-speed 0.13µ deep sub-micron process. Tested prototypes can be delivered in 4-5 weeks and production parts in 10-12 weeks.

Features and Benefits

• USB 2.0 HS On-the-Go PHY offers OTG, Device and Host functionality
• True ASIC gate count of 140 K to 1.8 M usable gates
• High-speed embedded SRAM of 233 Kb to 1.1 Mb
• Granular X-Cell™ Structured ASIC architecture for maximum routability and density
• Highly configurable RAM blocks of 9 Kb for excellent memory use efficiency
• Single port, dual port or FIFO configurations of RAM blocks
• Core operating voltage 1.2 V
• I/O voltages of 1.5 V, 1.8 V, 2.5 V and 3.3 V
• Output drive strengths of up to 16mA
• Flexible I/O pads that can be power, ground, input, output or bi-directional
• I/Os: LVTTL, LVCMOS, HSTL (1/2/3), SSTL (18/2/3), 840 Mb/s LVDS, RSDS, PCI, PCI-X, XOSC
• 250 MHz maximum global operating frequency
• Six PLLs with output frequency range of 10 MHz - 1 GHz
• Multiple DLLs with output frequency of up to 500 MHz
• Commercial and Industrial grade temperature libraries
• Packages from 56QFN to 456PBGA

USB Sub-System

The built-in, silicon proven USB 2.0 HS OTG PHY, in combination with ChipX validated, synthesizable processors and USB Host, Device and OTG controllers form a complete, interoperability proven, USB sub-system capable of achieving USB-IF compliance. Customers can also use their own USB controller and processor of choice where desired. The USB sub-system on the CX6200 family of products removes complexity and risk of IP selection and IP interoperability testing, enabling faster time to market.

The CX6200 product family builds on four generations of ChipX Structured ASIC products and provides the greatest level of flexibility in terms of I/O and memory configurations.

Design Flow

ChipX spends considerable development effort to ensure that taping out a design to a CX6200 Structured ASIC is simple, painless, and low risk. ChipX provides downloadable libraries on-line, for Magma, Synopsys, and Synplify ASIC synthesis tools.

Many customers prefer to hand off their RTL designs early and let ChipX perform the entire timing closure loop, including synthesis and final simulations. ChipX can also convert obsolete design netlists into prototypes rapidly and reliably.