CX6100 Structured ASIC

The CX6100 product family combines a built-in, silicon proven, industry standard PHY for PCI Express with the well-proven X-Cell™ Structured ASIC architecture, to provide industry-leading performance using the UMC eight-metal high-speed 0.13µ deep sub-micron process. Tested prototypes can be delivered in 4-5 weeks and production parts in 10-12 weeks.

Features and Benefits

• PCI Express PHY offers up to 8 lanes at 2.5 Gbps
• True ASIC gate count of 400 K to 1504K usable gates
• High-speed embedded SRAM of 270 Kb to 3132 Kb
• Granular X-Cell™ Structured ASIC architecture for maximum routability and density
• Highly configurable RAM blocks of 9 Kb for excellent memory use efficiency
• Single port, dual port or FIFO configurations of RAM blocks
• Core operating voltage 1.2 V
• I/O voltages of 1.5 V, 1.8 V, 2.5 V and 3.3 V
• Output drive strengths of up to 16 mA
• Flexible I/O pads that can be power, ground, input, output or bi-directional
• I/Os: LVTTL, LVCMOS, HSTL (1/2/3), SSTL (18/2/3), 840 Mb/s LVDS, RSDS, PCI, PCI-X, XOSC
• Silicon-proven DDR/DDR2 up to 400 Mbps/667 Mbps
• 250 MHz maximum global operating frequency
• Up to seven PLLs with output frequency range of 10 MHz - 1 GHz
• Multiple DLLs with output frequency of up to 500 MHz
• Commercial and Industrial grade temperature libraries
• 88 QFN and 144TFBGA packages are available for single-lane PCI Express applications. BGA packages from 256 to 1296 balls are available for more than 4-lane PCI Express applications
• Custom Structured ASIC configurations possible. (Discuss with ChipX)

 
PCI Express Sub-System

The built-in, silicon proven PCI Express PHY, in combination with ChipX validated, synthesizable processors and PCI Express Root Port, Endpoint and Bridge controllers form a complete, interoperability proven, PCI Express sub-system capable of achieving PCI-SIG compliance. Customers can also use their own PCI Express controller and processor of choice where desired. The PCI Express sub-system on the CX6100 family of products removes complexity and risk of IP selection and IP interoperability testing, enabling faster time to market. The CX6100 product family builds on four generations of ChipX Structured ASIC products and provides the greatest level of flexibility in terms of I/O and memory configurations.

Design Flow

ChipX spends considerable development effort to ensure that taping out a design to a CX6100 Structured ASIC is simple, painless, and low risk. ChipX provides downloadable libraries on-line, for Magma, Synopsys, and Synplify ASIC synthesis tools.

 Many customers prefer to hand off their RTL designs early and let ChipX perform the entire timing closure loop, including synthesis and final simulations. ChipX can also convert obsolete design netlists into prototypes rapidly and reliably.

Custom and New Structured ASIC Configurations

ChipX is always defining new Structured ASIC configurations driven by specific customers. New configurations can be built with no impact on schedule. Please inquire with ChipX if your requirements cannot be supported with the offering shown above.