CX3000 Structured ASIC

CX3000 Structured ASIC Datasheet

CX3000 Structured ASIC Product Brief

The CX3000 Structured ASIC family is based on 0.35µ technology using 2 layers of programmable metal, and supports performance levels up to 50 MHz. This family offers cost-effective solutions for designs with legacy requirements such as 5 V tolerance. Using ChipX's innovative architecture, low cost and rapid design turnaround time are built-in. The CX3000 product services those applications requiring 5 V capability in the networking, industrial, military and aerospace markets.

Features and Benfits

• 21 K to 200 K usable ASIC gates
• Up to 352 Kbits total SRAM configurable as single port/dual port or ROM
• Configurable I/O: PCI (3 V / 5 V)
• 5 V drive or 3.3 V with 5 V tolerance
• Up to 512 total pads
• 50 MHz general core logic operation, 100 MHz in constrained clock domains operation
• 4 low-jitter APLLs
• 5-6 week lead time for tested prototypes