ASIC Volume Production Without Breaking the Bank

ASIC Volume Production Without Breaking the Bank

Product Line Managers and ASIC Program Managers face the same fundamental problem: mixed-signal ASIC part prices may be affordable, but up-front costs are such that the total cost of ownership only makes sense for products that run in high volume. What if your market is slow to start?

A variety of options exists today, ranging from virtually zero Non-Recurring Engineering (NRE) cost, high component price Field Programmable Gate Arrays (FPGAs), to low NRE Structured ASIC, to lowest component cost but high NRE full mixed-signal Standard Cell ASIC. All of these options solve one or two of the problems identified above, but not all.

FPGAs offer the lowest barrier to entry. Attractions include low starting costs, on-the-fly field programmability, and decent performance. Newer FPGAs even include fast interfaces and other IP blocks that can help speed up development. In truly high volume, however, field programmability is typically no longer required, and the additional component expense becomes a significant barrier to profitability. Conversion to an ASIC is possible, as long as this path is planned for well in advance and the design does not use any of the proprietary IP offered by the FPGA vendors, since such IP is typically not available for porting to other silicon.

Structured ASIC, Platform ASIC, and a variety of similar technologies offer configurability through metal layers. NRE costs are higher than for FPGA, but substantially lower than for a full mixed-signal Standard Cell ASIC. Product changes can be made very quickly. Component size and therefore price, although much better than FPGA, is still not optimal, once again presenting a barrier to profitability when volume increases.

Mixed-signal Standard Cell ASIC or custom ASIC solutions offer the best performance and the smallest die size, but also require a significant up-front NRE investment that can range from hundreds of thousands to millions of dollars. In addition, mask preparation and production are time consuming, which slows down product market entry and increases the risk that requirements could change between product definition and market introduction.

Most smaller companies, or new product lines in large companies, have to start development with limited funds. The new product has to prove itself before additional funding will become available, either from investors or the parent company. Yet when the product becomes successful, features ultimately take a back seat to simple concerns of low component cost.

In the following pages, we present two development approaches that significantly reduce the time it takes to introduce a new mixed-signal ASIC and that increase the chances of having the right feature set for the market at the lowest cost.

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