ASIC Options ASIC Options |
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Many ASIC technologies and architectures have been developed in the past 30 years. The following are the most well-known ASIC types used in the industry: Standard Cell, Structured ASIC, Hybrid ASIC, Gate Array, Embedded Array, Side Chip and XPath solutions.
Standard Cell
Structured ASIC
Gate Array The Gate Array is made up of "basic cells," each cell containing some number of transistors and resistors. Using a cell library (gates, registers, etc.) and a macro library (more complex functions), the customer designs the chip, and ChipX industry standard software tools generate the interconnection masks. Some cells go wasted on Gate Array designs, which is the penalty for being able to benefit from fewer masks to build a chip. This technology has been rendered obsolete with the existence of Structured ASICs.
Embedded Array
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ChipX Standard Cell ASICs, which use a full set of masks for fabrication, are the approach of choice for very high volume, stable designs as well as highly complex designs requiring ultimate performance. Once a design has been proven in the market and has predictable production volumes, ChipX Standard Cell ASICs deliver the best efficiency and economy. Based on the customer's design, the required circuits are placed on the chip and connected using industry standard EDA software. Standard Cell ASICs can integrate mixed-signal IP elements from ChipX or third parties to create a System-on-Chip (SoC) device. Unlike Structured ASICs, Embedded Arrays or Gate Arrays, which start with partially fabricated wafers of repetitive blocks of unconnected standard elements, Standard Cell designs are created on blank wafers. The design therefore only includes the exact requirements of the application, leading to more efficient use of silicon area. The designer can adjust the number of routing layers to reach timing closure and balance die size with the number of metal layers used.
Structured ASICs, also known as Platform ASICs, are an enhanced form of Gate Arrays (see details below) that were invented in the early 1980s. Structured ASICs remove the complexity of custom silicon design by providing a fabric of configurable logic cell building blocks (or Structured Array), the ChipX X-Cell™, combined with easily configurable memory and I/O structures. Using only industry standard design automation tools, the logic portion of the design is configured on the ChipX Structured ASIC fabric (or array) using the top layers of metal, enabling the lower layers to be pre-built and used by multiple customer designs. By using this methodology, customers benefit from faster turnaround time and lower NREs compared with the Standard Cell ASIC methodology. Certain ChipX Structured ASIC families also include pre-validated mixed-signal IP, which reduces the risk of integration significantly as well as the development time. ChipX Structured ASICs offer the additional benefit of simple re-configuration, allowing very rapid design changes using industry standard routing and layout tools eliminating the need for tedious and often risky manual rework or Engineering Change Orders (ECO).
ChipX Hybrid ASICs are Standard Cell ASICs with an embedded IP core of configurable logic or Structured Array. This approach provides the smallest die size possible, while providing some flexibility for re-configuration of certain functions using metal layers only. The configurable logic core can be customized by ChipX to be any size or shape. The designer decides what function, or portion of the design, will be implemented in the configurable logic core. The designer may decide to save that space empty for future feature enhancements, saving time and cost of developing derivative products. Ideal applications for a Hybrid ASIC include encryption engines, compression algorithms, interface protocols and pre-standard implementations of a new or evolving standard.
Gate Arrays, the ancestors of ChipX Structured ASICs, consist simply of an array of gates, or “sea of gates”, in the pre-defined layers of metal. A ChipX Gate Array is partially finished with rows of transistors and resistors built-in but unconnected. Placing the top metal layers, which provide the connections between circuit elements, completes the design. These final masking stages are less costly than designing a Standard Cell ASIC.
Easily and seamlessly convert from Structured ASIC to Standard Cell when volumes increase. The ChipX XPath methodology allows you to have the best of both worlds—start in a Structured ASIC (SA) and benefit from fast time to market and easy, low cost silicon changes—then convert to Standard Cell for optimal economy, and get credit for most of the SA NRE. XPath offers continuity in production, full reuse of previous design efforts, and significant simplification of design flow. Only one signoff is required from the customer.